The scaling of VLSI circuits is a constant effort. With circuits become smaller and faster, improvement of device driving current becomes more important. Metal-oxide-semiconductor (MOS) transistor current is closely related to gate length, gate capacitance, and carrier mobility in the channel region. Shortening poly-gate length, increasing gate capacitance and increasing carrier mobility can improve the device currents of MOS devices. Gate length reduction is an ongoing effort in order to shrink circuit size. Increasing gate capacitance has also been achieved by efforts such as reducing the gate dielectric thickness, increasing the gate dielectric constant, and the like. In order to further improve device current, enhancing carrier mobility has also been explored.
Among efforts made to enhance carrier mobility, forming a stressed channel region is a known practice. Stress, sometimes referred to as strain, can enhance electron and hole mobility. The performance of a MOS device can be enhanced through a stressed-surface channel. This technique allows performance to be improved at a constant gate length, without adding complexity to circuit fabrication or design. Research has revealed that a tensile stress in the channel length direction can improve nMOS performance, and a compressive stress in the channel length direction can improve pMOS device performance.
A commonly used structure for applying compressive stress to the channel region of a pMOS device is shown in FIG. 1. A gate stack including a gate dielectric 4 and a gate electrode 6 is formed on a silicon substrate 1. SiGe regions 2 are formed in the substrate 1 with a channel region 8 therebetween. Typically, the formation of the SiGe regions 2 includes forming recesses in the silicon substrate 1 and epitaxially growing SiGe (with desired impurities) in the recesses. Since SiGe has a greater lattice constant then silicon, SiGe regions 2 press on the channel region 8, so that a compressive stress is developed in the channel region 8.
FIGS. 2 and 3 illustrate intermediate stages in the fabrication of the gate stack shown in FIG. 1. Typically, to form the gate stack, stacked layers, which include a gate dielectric layer, a gate electrode layer and a hard mask layer, are formed on the substrate 1. The stacked layers are then patterned to form gate dielectric 4, gate electrode 6, and hard mask 10. Hard masks have been extensively used in the formation of pMOS devices having SiGe regions. The patterning step may cause recesses 12 to be formed on the surface of the silicon substrate 1. In subsequent steps, as shown in FIG. 3, SiGe regions 2 are formed and the hard mask 10 is removed. Typically, the hard mask 10 comprises silicon nitride and is preferably removed using H3PO4. H3PO4 attacks silicon substrate 1 and results in deepened recesses 12. In prior art pMOS devices, if the hard mask is removed by H3PO4 after epitaxially growing SiGe regions 2, the depth Dp of the recesses 12 is easily greater than about 30 Å, and even achieving a depth of only 30 Å is difficult.
When doped SiGe regions are formed in pMOS devices, the impurities in the SiGe are more prone to diffusion during subsequent thermal processes. Diffused impurities deepen junction depths and compensate for pocket regions, resulting in the reduction of junction abruptness. Therefore, the short channel effects are adversely affected. If deeper recesses are formed under the spacers, the junction depth will be further increased, and the performance of the pMOS devices will be affected more.
Therefore, there is the need for a method for forming MOS devices, particularly pMOS devices, with reduced recesses in substrate regions close to the gate structure.